Processors in computer systems carrying out operations typically use a clock signal to regulate the timing of the operations. A clock signal has regularly timed transitions (at least one of rising or falling edges), such that operations can be carried out in the computer system in accordance with the timing of the transitions on the clock signal. In this way the frequency of the clock signal determines the frequency at which operations are performed in the computer system.
In some systems only rising edges of the clock signal are used to regulate the operations in the computer system. In such systems, the relative timing of the falling edges of the clock signal does not affect the timing of the operations in the computer system, provided that the rising edges are regularly timed. Therefore, clock signals with various mark-space ratios can be used. Similarly, in other systems only falling edges of the clock signal are used to regulate the operations in the computer system.
A chip in a computer system might malfunction in various ways if the clock signal is significantly slowed or stopped, even temporarily. In developing security measures, the inventor is aware that, for example, the security of data stored on a set-top-box chip may be compromised if the clock signal is significantly slowed or stopped. Security features on such set-top-box chips, or similar chips, may be compromised by significantly slowing down or stopping a clock which provides a clock signal to the chip. Detecting this condition provides a defence against such compromises to security features of chips.
It is an aim of the present invention to provide a method and circuit for detecting when the clock signal has been significantly slowed or stopped, allowing remedial action to be taken to prevent malfunction of the chip.